1. Technical Field of the Invention
The present invention relates to a method of manufacturing an insulated gate field-effect transistor. In particular, the present invention relates to a method of manufacturing a semiconductor device, which can be applied to a thin film transistor (TFT) with a gate overlapping structure.
2. Description of the Related Art
In a display device using a liquid crystal, a part with a large-screen over 20 inches, which is typified in a liquid crystal display TV, has been put to practical use. In recent years, a liquid crystal display device integrated with a driving circuit has been realized with a TFT in which a polycrystalline silicon film is used as an active layer.
However, a defect is pointed out that a TFT using a polycrystalline silicon film has a low withstanding pressure in drain junction to increase junction leak current (hereinafter, OFF-leak current). It is known that it is effective to form a lightly doped drain (LDD: Lightly Doped Drain) structure as measures for the defect.
The phenomenon is pointed out as a problem that high electric field is generated in the vicinity of the drain region, then, a generated hot carrier is trapped by a gate insulating film on the LDD region, and then, device characteristics such as threshold voltage are greatly fluctuated and lowered. In order to prevent the deterioration due to hot carriers, a TFT in which a gate electrode is overlapped with an LDD region is disclosed (for example, refer to Japanese Patent Laid-Open No. 2000-294787). The TFT with the gate overlapped LDD structure has higher current driving ability compared to a TFT with a normal LDD structure, and effectively eases the high electric field in the vicinity of the drain region to suppress the deterioration due to hot carriers.
However, in the case of the TFT with the gate overlapped LDD structure disclosed in the above-mentioned publication, after an impurity region for forming an LDD region is formed in a semiconductor layer, a gate electrode is overlapped with the LDD region. Accordingly, the portion overlapping with the gate electrode cannot be accurately formed along with the miniaturization of design rule.
On the other hand, as a method for manufacturing a TFT with a gate overlapping LDD structure in a self-aligning manner, the technique is disclosed that a conductive layer that has at least two layer laminated is subjected to exposure once and etching plural times to make the upper layer and the lower layer have different sizes, and then, ion doping is conducted with utilizing the differences in size and thickness to form an LDD region overlapped with a gate electrode in self-aligning manner (for example, refer to Japanese Patent Laid-Open No. 2002-14337).
Of course, it is necessary that a length of the LDD (a length with respect to the channel length) is optimized in accordance with a driving voltage of the TFT in order to maximally show the function of the LDD overlapped with the gate electrode as measures against the deterioration due to hot carriers. Namely, there is an optimum length for effectively easing the high electric field in the vicinity of the drain region.
The technique disclosed in the above-mentioned Patent Document 2 has two steps; the first step of etching a conductive layer that has two laminated layers into a tapered shape and the second step of selectively subjecting only the upper layer of the conductive layer in the tapered shape to anisotropic etching, and is characterized in that a taper angle is controlled to enable controlling the length of the LDD.
3. Problem Solved by the Invention
For not only the gate electrode but also an edge portion or a sidewall portion of a film, it makes an etching process into a tapered-shape in accordance with a mask pattern possible that dry etching is used to etch the object to be processed while recessing a width of the mask pattern at the same time. For that purpose, the selection of a kind of gas for etching, the regulation of bias voltage, and the selective ratio of the film to a material of the mask pattern are important matters.
In the conventional technique using a gate electrode that has a laminated structure of at least two layers, it is necessary that a taper angle (an angle with a surface) of an edge be decreased in the stage of processing the gate electrode in order to control a length of the LDD. For that purpose, the mask pattern needs to be largely recessed. It is necessary to make the film thickness thicker to leave a margin since etching is performed to recess the mask pattern, which results in a problem that a microscopic mask pattern cannot be formed.
With respect to an issue concerning the selective ratio in the etching process, the relationship between etching gas and a material of the object to be processed needs to be considered.
In order to drive a TFT with a channel length on the order of 10 μm at 10 to 20 V, the TFT needs to have an LDD with a length (a length of a portion overlapping with a gate electrode) at least 1 μm (preferably, at least 1.5 μm). In this case, it is necessary to form a taper angle of approximately 20° with respect to a titanium film with 0.5 μm in thickness according to the above-mentioned conventional technique. However, since titanium is hard to be subjected to taper processing, such small taper angle cannot be formed by dry etching.
The present invention uses inexpensive titanium instead of expensive tungsten, and a gate electrode comprises a laminate that has a first conductive layer comprising tantalum nitride and a second conductive layer comprising titanium or one of an alloy and a compound including titanium as its main component. Alternatively, there is a case where titanium nitride is further laminated on the second conductive layer as a third conductive layer.
With respect to the selective ratio in the etching process, it is an object of the present invention to provide a technique for giving design freedom in size of an LDD overlapped with a gate electrode, which is formed in a self-aligning manner, and in particular, for manufacturing with a TFT that have excellent resistance to hot carriers with high repeatability by performing an etching process under an etching condition that has a high selective ratio between a mask pattern and one of titanium, an alloy including titanium as its main component, a compound including titanium as its main component, and titanium nitride (mask pattern/conductive layer) in forming a first conductive layer pattern.